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sa7026 1.3ghz low voltage fractional-n dual frequency synthesizer objective specification supersedes data of 1998 apr 06 1998 oct 13 integrated circuits
philips semiconductors objective specification sa7026 1.3ghz low voltage fractional-n dual synthesizer 2 1998 oct 13 features ? low phase noise ? low power ? fully programmable main and auxiliary dividers ? normal & integral charge pumps outputs ? fast locking adaptive mode design ? internal fractional spurious compensation ? hardware and software power down applications ? 5001300 mhz wireless equipment ? cellular phones ? portable battery-powered radio equipment. general description the sa7026 bicmos device integrates programmable dividers, charge pumps and a phase comparator to implement a phase-locked loop. the device is designed to operate from 3 nicd cells, in pocket phones, with low current and nominal 3 v supplies. the synthesizer operates at vco input frequencies up to 1.3 ghz. the synthesizer has fully programmable main, auxiliary and reference dividers. all divider ratios are supplied via a 3-wire serial programming bus. separate power and ground pins are provided to the analog and digital circuits. the ground leads should be externally short-circuited to prevent large currents flowing across the die and thus causing damage. v ddcp could be greater than or equal to v dd . the charge pump current (gain) is fixed by an external resistance at pin r set (pin ) . only passive loop filters are used; the charge-pump operates within a wide voltage compliance range to provide a wider tuning range. sr01649 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 lock test v dd gnd rfin+ rfin gnd cp php phi gnd cp pon strobe data clock ref in + ref in rset auxin v ddcp pha 10 figure 1. pin configuration quick reference data symbol parameter conditions min. typ. max. unit v dd supply voltage v dd 2.7 5.5 v v ddcp analog supply voltage v ddcp v dd 2.7 5.5 v i ddcp +i dd supply current main and aux. on 7.5 8.8 ma i ddcp +i dd total supply current in power-down mode 1 m a f vco input frequency 500 1300 mhz f aux input frequency 10 550 mhz f ref crystal reference input frequency 10 40 mhz f pc maximum phase comparator frequency 4 mhz t amb operating ambient temperature 40 +85 c ordering information type number package type number name description version SA7026DK tssop20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot3601
philips semiconductors objective specification sa7026 1.3ghz low voltage fractional-n dual synthesizer 1998 oct 13 3 sr01496 clock data strobe rfin+ rfin ref in+ ref in auxin test load signals address decoder 2bit shift register 22bit shift register control latch latch main divider sm reference divider 2222 latch amp amp 15 16 6 5 19 18 17 12 2 latch aux divider phase detector phase detector comp pump bias pump current setting 13 v ddcp gnd 4 sa 10 3 gnd cp v dd rset gnd cp php phi lock pha pump bias 14 7 8 9 1 11 pon 20 figure 2. block diagram pinning symbol pin description lock 1 lock detect output test 2 test v dd 3 digital supply gnd 4 digital ground rfin+ 5 rf positive input to main divider rfin 6 rf negative input to main divider gnd cp 7 charge pump ground php 8 main normal chargepump phi 9 main integral chargepump gnd cp 10 charge pump ground symbol pin description pha 11 auxiliary chargepump output auxin 12 input to auxiliary divider v ddcp 13 charge pump supply voltage rset 14 external resistor from this pin to ground sets the chargepump current ref in 15 reference input ref in+ 16 reference input clock 17 programming bus clock input data 18 programming bus data input strobe 19 programming bus enable input pon 20 power down control
philips semiconductors objective specification sa7026 1.3ghz low voltage fractional-n dual synthesizer 1998 oct 13 4 characteristics v ddcp = v dd = +3.0v, t amb = +25 c; unless otherwise specified. symbol parameter conditions min. typ. max. unit supply; pins 3, 13 v dd digital supply voltage 2.7 5.5 v v ddcp analog supply voltage v ddcp = v dd 2.7 5.5 v i ddtotal synthesizer operational digital supply current v dd = +3.0 v (with main and aux on) 7.5 8.8 ma i standby total supply current in power-down mode logic levels 0 or v dd 1 tbd m a rfin main divider input; pins 5, 6 f vco vco in p ut frequency 500 1300 mhz f vco vco in ut frequency 500 1300 mhz v rfi ( ) ac cou p led in p ut signal level r =50 w ; max limit is 18 0 dbm v rfin(rms) ac - coupled input signal level r s = 50 w ; max . limit is indicative 18 0 dbm indicati v e z irfin input impedance (real part) f vco = 2.0 ghz tbd k w c irfin typical pin input capacitance indicative, not tested tbd pf n m main divider ratio 512 65535 f pcmax maximum loop comparison frequency indicative, not tested 4 mhz aux reference divider input; pins 12 f auxin input frequency range 10 550 mhz v auxi ac cou p led in p ut signal level r s =50 w ; max. limit is 18 0 dbm v auxin ac - coupled input signal level r s 50 w max. limit is indicative 80 636 mvpp z auxin input impedance (real part) f vco =500 mhz tbd k w c auxin typical pin input capacitance indicative, not tested tbd pf n aux auxiliary division ratio 128 16384 reference divider input; pins 15, 16 f refin input frequency range from crystal 10 40 mhz vrfin ac-coupled input signal level r s =50 w ; max. limit is 360 1300 mvpp g s indicative z refin input impedance (real part) tbd k w c refin typical pin input capacitance indicative, not tested tbd pf r ref reference division ratio sa=sm=o000o 4 1023 charge pump current setting resistor input; pin 14 r set external resistor from pin 3 to ground 6 7.5 24 k w v set regulated voltage at pin 3 r set =7.5 k w 1.25 v charge pump outputs (including fractional compensation pump); pins 8, 9, 11; r set =7.5 k w , fc=80 icp chargepump current ratio to iset current gain i ph /i set 15 +15 % i match sink-to-source current matching v ph =1/2 v ddcp 10 +10 % i zout output current variation versus v ph 2 v ph in compliance range 10 +10 % i lph charge pump off leakage current v cp =1/2 v cc 10 +10 na v ph charge pump voltage compliance 0.7 v ddcp 0.8 v
philips semiconductors objective specification sa7026 1.3ghz low voltage fractional-n dual synthesizer 1998 oct 13 5 symbol unit max. typ. min. conditions parameter phase noise c/n synthesizer's contribution to close-in-phase noise of 1300 mhz rf signal at 1 khz offset. fref=19.44mhz; fcomp=240khz indicative, not tested 77 dbc hz interface logic input signal levels; pins 3, 15, 16, 18, 19, 20 v ih high level input voltage 0.7*v dd v dd +0.3 v v il low level input voltage 0.3 0.3*v dd v i bias input bias current logic 1 or logic 0 5 +5 m a lock detect output signal (in push/pull mode); pin 1 v ol low level output voltage i sink = 2ma 0.4 v v oh high level output voltage i source = 2ma v dd 0.4 v notes: 1. i set = v set r set bias current for charge pumps. 2. the relative output current variation is defined thus: i out i out 2 . (i 2 i 1 ) i(i 2 i 1 )i ; with v 1 0.7v, v 2 v ddcp 0.8v (see figure 3.) i 2 i 1 i 2 i 1 v 1 v 2 current voltage sr00602 figure 3. relative output current variation
philips semiconductors objective specification sa7026 1.3ghz low voltage fractional-n dual synthesizer 1998 oct 13 6 limiting values in accordance with the absolute maximum rating system (iec 134). symbol parameter min. max. unit v dd digital supply voltage 0.3 +5.5 v v ddcp analog supply voltage 0.3 +5.5 v d v ddcp v dd difference in voltage between v ddcp and v dd (v ddcp v dd ) 0.3 +2.8 v v n voltage at pins 1, 2, 5, 6, 12, 15 to 20 0.3 v dd + 0.3 v v 1 voltage at pin 8, 9, 13 0.3 v ddcp + 0.3 v d v gnd difference in voltage between gnd cp and gnd (these pins should be connected together) 0.3 +0.3 v p tot total power dissipation tbd mw t stg storage temperature 55 +125 c t amb operating ambient temperature 30 +85 c t j maximum junction temperature tbd c handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. thermal characteristics symbol parameter value unit r th ja thermal resistance from junction to ambient in free air 120 k/w
philips semiconductors objective specification sa7026 1.3ghz low voltage fractional-n dual synthesizer 1998 oct 13 7 functional description main fractional-n divider the rfin input (pins 5 and 6) drive a pre-amplifier to provide the clock to the first divider stage. for single ended operation, the signal should be fed to one of the inputs while the other one is ac grounded. the pre-amplifier has a high input impedance, dominated by pin and pad capacitance. the circuit operates with signal levels from 18dbm to +0dbm, and at frequencies as high as 2.5 ghz. the divider consists of a fully programmable bipolar prescaler followed by a cmos counter. divide ratios (512 to 65536) allow a minimum phase comparison frequency of 25khz at 2.5 ghz rf. at the completion of a main divider cycle, a main divider output pulse is generated which will drive the main phase comparator. also, the fractional accumulator is incremented by the value of nf. the accumulator works with modulo q set by fmod. when the accumulator overflows the overall division ratio n will be increased by 1 to n + 1, the average division ratio over q main divider cycles (either 5 or 8) will be nfrac n nf q the output of the main divider will be modulated with a fractional phase ripple. the phase ripple is proportional to the contents of the fractional accumulator and is nulled by the fractional compensation charge pump. the reloading of a new programming word is synchronized to the state of the main divider to avoid introducing a phase disturbance. auxiliary divider the auxiliary divider consists of a divider with fully programmable values between 128 and 16384. the auxin input, pin 13, drives a pre-amplifier to provide the clock to the first divider stage. the auxin negative input is internally connected to ground. the pre-amplifier has a high input impedance, dominated by pin and pad capacitance. the circuit operates with signal levels from 18dbm to +0dbm (80 to 636 mvpp), and at frequencies as high as 550 mhz. the divider consists of a fully programmable bipolar prescaler followed by a cmos counter. the divide ratios allow a minimum phase comparison frequency of 25khz at 550 mhz rf. reference divider the reference divider consists of a divider with programmable values between 4 and 1023 followed by a three bit binary counter. the 3 bit sm (sa) register (see figure 4) determines which fo the 5 output pulses are selected as the main (auxiliary) phase detector input. phase detector the reference and main (aux) divider outputs are connected to a phase/frequency detector that controls the charge pump. the pump current is set by a an external resistor. the dead zone (caused by finite time taken to switch the current sources on or off) is cancelled by forcing the pumps on for a minimum time at every cycle (backlash time) providing improved linearity. sr01415 divide by r /2 /2 /2 /2 /2 reference input sm=o000o sm=o001o sm=o010o sm=o011o sm=o100o sa=o100o sa=o011o sa=o010o sa=o001o sa=o000o main phase detector auxiliary phase detector figure 4. reference divider
philips semiconductors objective specification sa7026 1.3ghz low voltage fractional-n dual synthesizer 1998 oct 13 8 sr01451 r x p n ref divider aux/main divider d q clk a1o r d r clk a1o x q n p t v dda gnd ph v ssa ptype charge pump ntype charge pump r inr inr i ph figure 5. phase detector struction with timing
philips semiconductors objective specification sa7026 1.3ghz low voltage fractional-n dual synthesizer 1998 oct 13 9 main output charge pumps and fractional compensation currents. the main charge pumps on pins php and phi are driven by the main phase detector and the charge pump current values are determined by the current at pin rset. the fractional compensation is derived from the current at rset, the contents of the fractional accumulator frd and by the program value of the fdac. the timing for the fractional compensation is derived from the main divider. see table of charge pump ratios. principle of fractional compensation the fractional compensation is designed into the circuit as a means of reducing or eliminating fractional spurs that predominate when the accumulator rolls over and the main divider counts one extra rf input cycle (+1, swallows a cycle). since i comp is the compensation current and i pump is the pump current, for each charge pump, i pump_total = i pump + i comp . the theoretical values for fdac are: 128 for fmod = 1 (modulo 5) and 80 for fmod = 0 (modulo 8). fractional division will cause the pump to output a charge that is compensated for in order to reduce fractional spurs. this compensation is done by sourcing a small current, i a , see figure 7, that is proportional to the fractional error phase. figure 6 shows that for proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple. this means i pump *q=i comp *128, where q equals fractional-n modulus e.g., 2/5 for nf = 2 and fmod = 1. the fractional compensation current is derived from the main charge pump in that it follows all the current scaling through external resistor setting, rn, programming or speed-up operation. for a given pump, i comp = ( i pump / 128 ) * ( fdac / 5*128) * frd frd is the fractional accumulator value. sr01416 reference r main m divide ratio detector output accumulator fractional compensation current output on pump n n n+1 n n+1 241 3 0 pulse width modulation pulse level modulation ma m a figure 6. waveforms for nf = 2, fraction = 0.4 fig 6. shows that for a proper fractional compensation, the area of the fractional compensation current pulse must be equal to the area of the charge pump ripple output. sr01682 f rf 1930.140 mhz main divider n = 8042 fractional accumulator f ref 240 khz 240.016 khz i a i c loop filter & vco figure 7. current injection concept
philips semiconductors objective specification sa7026 1.3ghz low voltage fractional-n dual synthesizer 1998 oct 13 10 auxiliary output charge pumps the auxiliary charge pumps on pin pha are driven by the auxiliary phase detector and the current value is determined by the ext ernal resistor attached to pin r set . main and auxiliary chargepump currents cp1 cp0 i pha i php i phpsu i phi 0 0 1.5xlset 3xiset 15xlset 36xlset 0 1 0.5xlset 1xlset 5xlset 12xlset 1 0 1.5xlset 3xlset 15xlset 0 1 1 0.5xlset 1xlset 5xlset 0 notes 1. i set = vset / rset : bias current for charge pumps. 2. cp1 is used to disable the phi pump, i php_su is the total current at pin php during speed up condition. lock detect the output lock maintains a logic `1' when the auxiliary phase detector anded with the main phase detector indicates a lock condition. the lock condition for the main and auxiliary synthesizers is defined as a phase difference of less than 1 period of the frequency at the input ref in+, . one counter can fulfill the lock condition when the other counter is powered down. out of lock (logic '0') is indicated when both counters are powered down. power-down mode the power-down signal can be either hardware (pon) or software (pd). the pon signal is exclusively ored with the pd bits. if pon = 0, then the part is powered up when pd = 1. pon can be used to invert the polarity of the software bit pd. when the synthesizer is reactivated after the power-down the main and reference dividers are synchronized to avoid possibility of random phase errors on power-up.
philips semiconductors objective specification sa7026 1.3ghz low voltage fractional-n dual synthesizer 1998 oct 13 11 serial programming bus the serial input is a 3-wire input (clock, strobe, data) to program all counter divide ratios, fractional compensation dac, selection and enable bits. the programming data is structured into 24 bit words; each word includes 2 address bits. figure 8 shows the timing diagram of the serial input. when the strobe goes active high, the clock is disabled and the data in the shift register remains unchanged. depending on the 2 address bits the data is latched into different working registers or temporary registers. in order to fully program the synthesizer, 3 words must be sent: c, b, and a. table 1 shows the format and the contents of each word. the d word is for testing purposes only. the data for the fractional compensation dac, fc is stored by the b word in temporary registers. when the a word is loaded, the data of these temporary registers is loaded together with the main divider ratio. serial bus timing characteristics. see figure 8. v dd = v ddcp =+3.0v; t amb = +25 c unless otherwise specified. symbol parameter min. typ. max. unit serial programming clock; clk t r input rise time 10 40 ns t f input fall time 10 40 ns t cy clock period 100 ns enable programming; strobe t start delay to rising clock edge 40 ns t w minimum inactive pulse width 1/fcomp ns t su;e enable set-up time to next clock edge 20 ns register serial input data; data t su;dat input data to clock set-up time 20 ns t hd;dat input data to clock hold time 20 ns application information sr01417 clk data strobe msb lsb address t su;dat t hd;dat t r t w t f t su;e t start t cy figure 8. serial bus timing diagram
philips semiconductors objective specification sa7026 1.3ghz low voltage fractional-n dual synthesizer 1998 oct 13 12 data format table 1. format of programmed data last in msb serial programming format first in lsb p23 p22 p21 p20 ../.. ../.. p1 p0 table 2. a word, length 24 bits last in msb lsb first in address fmod fractional-n main divider ratio spare 0 0 fm nf2 nf1 nf0 n15 n14 n13 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 sk1 sk2 default: 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 a word select fixed to 00. fractional modulus select fm 0 = modulo 8, 1 = modulo 5. fractional-n increment nf2..0 fractional n increment values 000 to 111. n-divider n0..n15, main divider values 512 to 65535 allowed for divider ratio. table 3. b word, length 24 bits address reference divider lock pd fractional compensation dac 0 1 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 l1 l0 main aux fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 default: 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 1 0 1 0 0 0 0 b word select fixed to 01 r-divider r0..r9, reference divider values 4 to 1023 allowed for divider ration. lock detect output l1 l0 0 0 combined main, aux. lock detect signal present at the lock pin (push/pull). 0 1 combined main, aux, lock detect signal present at the lock pin (open drain). 1 0 main lock detect signal present at the lock pin. 1 1 auxiliary loop lock detect signal present at the lock pin. when auxiliary loop and main loop are in power down mode, the lock indicator is low. power down main = 1: power to n-divider, reference divider, main charge pumps, main = 0 to power down. aux = 1: power to aux divider, reference divider, aux charge pump, aux = 0 to power down. fractional compensation fc7..0 fractional compensation charge pump current dac, values 0 to 255. recommended values: fc = 80 for mod 8; fc = 128 for mod 5. table 4. c word, length 24 bits address auxiliary divider cp sm sa 1 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 cp1 cp0 sm2 sm1 sm0 sa2 sa1 sa0 default 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 0 0 0 0 0 0 c word select fixed to 10 a-divider a0..a13, auxiliary divider values 128 to 16384 allowed for divider ratio. charge pump current ratio cp1, cp0: charge pump current ratio, see table of charge pump currents. main comparison select sm comparison divider select for main phase detector. aux comparison select sa comparison divider select for auxiliary phase detector. table 5. d word, length 24 bits address synthesizer test bits synthesizer test bits 1 1 0 tspu default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tspu: speed up forces the synthesizer charge pump in speed-up mode all the time. note : all test bits must be set to 0 for normal operation.
1.3ghz low voltage dual fractional-n frequency synthesizer philips semiconductors objective specification sa7026 1998 oct 13 13 tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1
1.3ghz low voltage dual fractional-n frequency synthesizer philips semiconductors objective specification sa7026 1998 oct 13 14 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a.
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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